<span style="font-size:11.0pt;mso-bidi-font-size: 10.0pt;font-family:" times="" new="" roman";mso-fareast-font-family:"times="" roman";="" mso-ansi-language:en-gb;mso-fareast-language:en-us;mso-bidi-language:ar-sa"="" lang="EN-GB">VLSI implementation of high throughput MIMO OFDM transceiver for 4^th generation systems</span>

Abstract

This paper aims to maximize throughput by minimizing power as minimum as possible. Scores of optimization techniques such as FFT, IFFT and memory optimization are available for reducing power of mobile OFDM systems. An approach for achieving reduction in power of MIMO OFDM system by optimizing FFT architecture is addressed in this paper. Memory references in MIMO OFDM transceiver are costly due to their long delay and high power consumption. To implement fast Fourier transform (FFT) algorithms on MIMO OFDM, involves many memory references to access butterfly inputs and twiddle factors. Conventional FFT implementations require unused memory references to load the same twiddle factors for butterflies from different stages in FFT diagrams. To minimize memory references due to twiddle factors for implementing FFT algorithms in MIMO OFDM systems, memory reference reduction method is incorporated here. Twiddle factor is calculated using binary scaling technique. The proposed FFT structure is the combination of memory reference reduction method with binary scaling technique and Radix-4 booth multiplier. Here multipliers in FFT are realized with shifters, adders and subtractors. The proposed structure is evaluated using performance parameters such as BER and SNR. Structural realization and analysis pertaining to timing, power and throughput are implemented in Virtex-4 and analysis is carried out in Altera respectively.