Please use this identifier to cite or link to this item:
http://nopr.niscpr.res.in/handle/123456789/1802| Title: | Implementation of improved error trapping decoder for multiple error correcting cyclic codes in a soft core processor |
| Authors: | Gayen, S B Dam, B Patranabis, D |
| Keywords: | Error trapping decoder;Kasami decoding algorithm;Soft core processor |
| Issue Date: | Aug-2008 |
| Publisher: | CSIR |
| Abstract: | This paper presents implementation of Tadao Kasami decoding algorithm for improved error trapping decoding and firmware realization details. Algorithm has been applied to cyclic (n, k) codes [Golay (23, 12) and BCH (31, 16)] for triple error correction. Microblaze 32-bit soft core processor was used with a Xilinx Spartan3 FPGA. To test decoder functionality, a test procedure with all possible error combination is devised. Profiling of execution time with no error and with error is presented along with hardware resource utilization of FPGA. |
| Page(s): | 574-578 |
| ISSN: | 0022-4456 |
| Appears in Collections: | JSIR Vol.67(08) [August 2008] |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| JSIR 67(8) 574-578.pdf | 83.89 kB | Adobe PDF | View/Open |
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