Please use this identifier to cite or link to this item: http://nopr.niscpr.res.in/handle/123456789/27719
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dc.contributor.authorRavichandran, V-
dc.contributor.authorVenkatesan, G K D Prasanna-
dc.date.accessioned2014-04-07T04:26:16Z-
dc.date.available2014-04-07T04:26:16Z-
dc.date.issued2014-04-
dc.identifier.issn0975-1084 (Online); 0022-4456 (Print)-
dc.identifier.urihttp://hdl.handle.net/123456789/27719-
dc.description209-213en_US
dc.description.abstractNoC (network On Chip) is an efficient approach to design the communication subsystem between IP Cores in SoC (System on Chip). In this paper a communication infrastructure design using CDMA (Code division multiple access) based shared bus architecture for core-to-core communication in NoC is presented. CDMA has been proposed as an alternative way for interconnect of IP cores in a SoC design, or as a solution for interconnecting modules within a system realized in several PCBs. Compared to a conventional TDMA-based bus this paper present how a multiprocessor system can benefit from the use of concurrent data transfers. The simulation of the system using VHDL code is carried out. The performance of the system and is evaluated. en_US
dc.language.isoen_USen_US
dc.publisherNISCAIR-CSIR, Indiaen_US
dc.rights CC Attribution-Noncommercial-No Derivative Works 2.5 Indiaen_US
dc.sourceJSIR Vol.73(04) [April 2014]en_US
dc.subjectCDMA busen_US
dc.subjectDecodingen_US
dc.subjectEncodingen_US
dc.subjectNOCen_US
dc.subjectWalsh codeen_US
dc.titleNetwork on Chip with CDMA Techniqueen_US
dc.typeArticleen_US
Appears in Collections:JSIR Vol.73(04) [April 2014]

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