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http://nopr.niscpr.res.in/handle/123456789/27719Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Ravichandran, V | - |
| dc.contributor.author | Venkatesan, G K D Prasanna | - |
| dc.date.accessioned | 2014-04-07T04:26:16Z | - |
| dc.date.available | 2014-04-07T04:26:16Z | - |
| dc.date.issued | 2014-04 | - |
| dc.identifier.issn | 0975-1084 (Online); 0022-4456 (Print) | - |
| dc.identifier.uri | http://hdl.handle.net/123456789/27719 | - |
| dc.description | 209-213 | en_US |
| dc.description.abstract | NoC (network On Chip) is an efficient approach to design the communication subsystem between IP Cores in SoC (System on Chip). In this paper a communication infrastructure design using CDMA (Code division multiple access) based shared bus architecture for core-to-core communication in NoC is presented. CDMA has been proposed as an alternative way for interconnect of IP cores in a SoC design, or as a solution for interconnecting modules within a system realized in several PCBs. Compared to a conventional TDMA-based bus this paper present how a multiprocessor system can benefit from the use of concurrent data transfers. The simulation of the system using VHDL code is carried out. The performance of the system and is evaluated. | en_US |
| dc.language.iso | en_US | en_US |
| dc.publisher | NISCAIR-CSIR, India | en_US |
| dc.rights | CC Attribution-Noncommercial-No Derivative Works 2.5 India | en_US |
| dc.source | JSIR Vol.73(04) [April 2014] | en_US |
| dc.subject | CDMA bus | en_US |
| dc.subject | Decoding | en_US |
| dc.subject | Encoding | en_US |
| dc.subject | NOC | en_US |
| dc.subject | Walsh code | en_US |
| dc.title | Network on Chip with CDMA Technique | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | JSIR Vol.73(04) [April 2014] | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| JSIR 73(4) 209-213.pdf | 241.97 kB | Adobe PDF | View/Open |
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