A new cascadable CMOS voltage squarer circuit and its application: Four-quadrant analog multiplier

Abstract

A new cascadable CMOS based voltage squarer circuit having voltage input/current output and its analog four-quadrant multiplier application are presented. The proposed structure has high input impedance and high output impedance; thus, it can be easily connected to other circuits without requiring any extra buffers. Moreover, its two symmetrical bias voltages have high input impedances; accordingly, bias voltages can be easily connected without requiring additional circuits. Another advantage of the proposed circuit is its low power consumption. It consists of only six MOS transistors. However, it needs several active component matching constraints. Some SPICE simulation and experimental test results are included to confirm the proposed theory.