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http://nopr.niscpr.res.in/handle/123456789/29804Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sarkar, B C | - |
| dc.contributor.author | De, B | - |
| dc.contributor.author | Sarkar, S | - |
| dc.date.accessioned | 2014-11-07T08:57:15Z | - |
| dc.date.available | 2014-11-07T08:57:15Z | - |
| dc.date.issued | 1996-10 | - |
| dc.identifier.issn | 0975-1017 (Online); 0971-4588 (Print) | - |
| dc.identifier.uri | http://hdl.handle.net/123456789/29804 | - |
| dc.description | 185-190 | en_US |
| dc.description.abstract | A new phase locked loop (PIL)-based data clock recovery circuit having non-linear error control characteristics has been proposed. Its performance has been studied by analytical means, by numerically solving the system eqution using computer, and by hardware experiment in the radio frequency band. Different performance-measuring parameters of the system such as acquisition range and transient response time obtained by different methods confirm the improved response of the proposed circuit compared to the conventional system. | en_US |
| dc.language.iso | en_US | en_US |
| dc.publisher | NISCAIR-CSIR, India | en_US |
| dc.rights |  CC Attribution-Noncommercial-No Derivative Works 2.5 India | en_US |
| dc.source | IJEMS Vol.03(5) [October 1996] | en_US |
| dc.title | Structure and performance of a new data clock time recovery phase locked loop | en_US |
| dc.type | Article | en_US |
| Appears in Collections: | IJEMS Vol.03(5) [October 1996] | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| IJEMS 3(5) 185-190.pdf | 826 kB | Adobe PDF | View/Open |
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