Layer Router for Grayscale Stego - A Hardware Architecture on FPGA and ASIC Platforms

Abstract

In the present era of secret communication, steganography has obtained a significant place in information security by means of offering variety of techniques for cleverly hiding the information. In addition to the existing hardware stego algorithms, an adaptive block hardware stego system has been proposed in this paper which follows a shortest path algorithm for performing secret concealment in grayscale images. The proposed image steganographic hardware architecture which adopts traversal procedures predominant in area routing has been implemented both in Stratix III FPGA as well as ASIC Platforms.