Please use this identifier to cite or link to this item: http://nopr.niscpr.res.in/handle/123456789/31748
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dc.contributor.authorSrivastava, Pragya-
dc.contributor.authorIslam, Aminul-
dc.date.accessioned2015-07-09T04:15:44Z-
dc.date.available2015-07-09T04:15:44Z-
dc.date.issued2015-06-
dc.identifier.issn0975-1017 (Online); 0971-4588 (Print)-
dc.identifier.urihttp://hdl.handle.net/123456789/31748-
dc.description261-267en_US
dc.description.abstractDue to aggressive scaling, CMOS technology is facing a few critical issues. Few of them are variability, subthreshold leakage, gate leakage, and short-channel effects. Variability has become a metric of equal importance as power, delay, and area in deep submicron technology node. Therefore, this paper carries out power delay product (PDP) variability analysis of MOS current mode logic (MCML) and CMOS inverter/buffer and XOR/XNOR circuits in addition to propagation delay (tp), average power (PWR), power-delay product (PDP) and energy-delay product (EDP) analysis at 16-nm technology node. MCML inverter/buffer (XOR/XNOR) circuits prove their robustness by exhibiting 1.66× (1.82×) improvement in PDP variability at nominal supply voltage of VDD = 0.7 V. Therefore, this work realizes XOR/XNOR circuit using carbon nanotube field effect transistor (CNFET). CNFET based MCML XOR/XNOR circuit exhibits lower tp (by 91.20×), lower PDP (by 3.15×) and lower EDP (by 287.69×) compared to MOSFET based MCML XOR/XNOR at nominal VDD.en_US
dc.language.isoen_USen_US
dc.publisherNISCAIR-CSIR, Indiaen_US
dc.rights CC Attribution-Noncommercial-No Derivative Works 2.5 Indiaen_US
dc.sourceIJEMS Vol.22(3) [June 2015]en_US
dc.subjectCNFETen_US
dc.subjectEDPen_US
dc.subjectMOS current mode logicen_US
dc.subjectPower delay Producten_US
dc.subjectPropagation delay (tp)en_US
dc.subjectVariabilityen_US
dc.titleCNFET-based design of resilient MCML XOR/XNOR circuit at 16-NM technology nodeen_US
dc.typeArticleen_US
Appears in Collections:IJEMS Vol.22(3) [June 2015]

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