Please use this identifier to cite or link to this item:
http://nopr.niscpr.res.in/handle/123456789/67210| metadata.dc.identifier.doi: | https://doi.org/10.56042/ijpap.v64i1.14342 |
| Title: | Ku-Band Ring Oscillator Architecture with Frequency Tuning and Phase Noise Mitigation |
| Authors: | Arya, Rachana K Singh, B |
| Keywords: | Voltage control ring oscillator;Delay;45 nm Technology;Noise margin;Power utilisation |
| Issue Date: | Jan-2026 |
| Publisher: | NIScPR-CSIR, India |
| Abstract: | This study presents a 14.5 GHz Ku-band Voltage-Controlled Ring Oscillator (VCRO) designed in 45 nm CMOS technology, operating with a supply voltage from 0.1V to 1.3V and covering a frequency range of 0.034 GHz to 16 GHz. At 1.3V, the simulated delay time is 0.04 ns, while at 1V, it increases to 0.068 ns. The design achieves a phase noise of –80.17 dBc/Hz at 1 MHz offset and –105.3 dBc/Hz at 100 MHz offset, with a power consumption of only 3.26 μW at 1V. The five-stage ring oscillator demonstrates a 23.5% tuning range, spanning 11.2 GHz to 16 GHz. By utilising 45 nm CMOS scaling, the proposed VCRO attains enhanced power efficiency, frequency stability, and integration capability. The delay-stage optimisation effectively minimises phase noise while preserving a broad tuning range. Compared with existing designs, this oscillator exhibits superior frequency stability and power-performance trade-off, efficiently balancing phase noise, tuning range, and power consumption. Despite challenges from device variability and limited voltage headroom in advanced nodes, the proposed VCRO sustains low phase noise and stable frequency operation, establishing a robust low-power solution for Ku-band and next-generation CMOS communication systems. |
| Page(s): | 7-17 |
| ISSN: | 0975-1041 (Online) ; 0019-5596 (Print) |
| Appears in Collections: | IJPAP Vol.64(01) [January 2026] |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| IJPAP 64(01) 7-17.pdf | 2.25 MB | Adobe PDF | View/Open |
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