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http://nopr.niscpr.res.in/handle/123456789/68620| metadata.dc.identifier.doi: | https://doi.org/10.56042/ijems.v33i03.23089 |
| Title: | Design and characteristics exploration of an InAs-source-based electrostatic doped vertical nanowire TFET |
| Authors: | Bhardwaj, Anjana Das, Amit Yadav, Shivani Dhillon, Yuvika |
| Keywords: | Dopingless transistor;InAs/Si interface;Indium arsenide source;Nanowire transistor;Silvaco TCAD;VNW-TFET |
| Issue Date: | Jun-2026 |
| Publisher: | NIScPR-CSIR, India |
| Abstract: | In this manuscript, the nanotube structure with vertical architecture and an indium arsenide-based source has been proposed. In the proposed device, the electrostatic doping (ED) has been applied to eliminate the doping ambiguities like expensive thermal budget (ETB) and random dopant fluctuation (RDF). RF and analogue metrics, including transconductance (gm), drain current (ID), output conductance (gd), output characteristics (ID–VDS), cut-off frequency (fT), and gate capacitance (CGG), have been utilized to analyze the device characteristics. The structural parameters of the device, like energy band, electric field, potential, and carrier concentration,have also been investigated. The InAs-based source electrostatic-doped VNW-TFET (InAs-S-ED-VNW-TFET) has shown better performance than the conventional or Si-based source VNW-TFET (Si-S-ED-VNW-TFET) due to its higher mobility, lower bandgap, and lower effective mass, resulting in a higher tunneling rate. With the inclusion of electrostatic doping, uniform doping has been achieved throughout the device. The device has been optimized by achieving a steeper subthreshold slope of 19.8 mV/Dec., higher ON current 8.99μA/μm, and higher ON/OFF current ratio of 1.23 × 1013. |
| Page(s): | 306-311 |
| ISSN: | 0975-1017 (Online) ; 0971-4588 (Print) |
| Appears in Collections: | IJEMS Vol.33(03) June |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| IJEMS Vol.33(3) 306-311.pdf | 1.81 MB | Adobe PDF | View/Open |
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