A novel logarithmic prefix adder with minimized power delay product

Abstract

Parallel prefix addition is a technique for speeding up binary addition. Classical parallel prefix adder structures developed so far are optimized for logic depth, area, fan-out and interconnect count of logic circuits. Due to continuing integrating intensity and growing needs of portable devices, low-power and high-performance designs are of prime importance. A new technique, proposed for performing parallel prefix addition, has least power delay product in comparison with its peer prefix adder structures. Tanner EDA tool was used for simulation in TSMC 180 nm technology.