On the jitter performance of a quantizer based modified DPLL

Abstract

The paper examines the effect of an additional derivative control signal (ADCS) on the steady state phase jitter characteristics of first and second order digital phase locked loops (DPLLs) having a finite level quantizer. It has been shown that the ADCS reduces the steady state phase jitter variance particularly when the DPLL gain parameters are high and the input signal has large frequency detuning. Further, a prefixed amount of SSPJ variance can be achieved in presence of the ADCS for a loop with a quantizer having lesser number of levels. The simulation results obtained have been qualitatively interpreted.