Please use this identifier to cite or link to this item:
http://nopr.niscpr.res.in/handle/123456789/27719| Title: | Network on Chip with CDMA Technique |
| Authors: | Ravichandran, V Venkatesan, G K D Prasanna |
| Keywords: | CDMA bus;Decoding;Encoding;NOC;Walsh code |
| Issue Date: | Apr-2014 |
| Publisher: | NISCAIR-CSIR, India |
| Abstract: | NoC (network On Chip) is an efficient approach to design the communication subsystem between IP Cores in SoC (System on Chip). In this paper a communication infrastructure design using CDMA (Code division multiple access) based shared bus architecture for core-to-core communication in NoC is presented. CDMA has been proposed as an alternative way for interconnect of IP cores in a SoC design, or as a solution for interconnecting modules within a system realized in several PCBs. Compared to a conventional TDMA-based bus this paper present how a multiprocessor system can benefit from the use of concurrent data transfers. The simulation of the system using VHDL code is carried out. The performance of the system and is evaluated. |
| Page(s): | 209-213 |
| ISSN: | 0975-1084 (Online); 0022-4456 (Print) |
| Appears in Collections: | JSIR Vol.73(04) [April 2014] |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| JSIR 73(4) 209-213.pdf | 241.97 kB | Adobe PDF | View/Open |
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