Please use this identifier to cite or link to this item:
http://nopr.niscpr.res.in/handle/123456789/33111| Title: | Design of Low Drop-Out voltage regulator |
| Authors: | Naidu, K J Kittur, H M Avinash, P |
| Keywords: | Analog circuits;Error amplifier;Dc-Dc regulators and LDO |
| Issue Date: | Nov-2015 |
| Publisher: | NISCAIR-CSIR, India |
| Abstract: | An essential component of today’s battery powered SoC’s are power management systems which include Low Drop-Out (LDO) voltage regulators. LDO voltage regulators improve battery’s power efficiency and life. In this paper design and analysis of an LDO voltage regulator is presented. The designed LDO voltage regulator is designed with self-compensated error amplifier. It provides 30mA load current with a stable 1.6V output voltage. It consumes 172μA quiescent current and has a power efficiency of 88.38 % with dropout voltage of 200mV. |
| Page(s): | 641-644 |
| ISSN: | 0975-1084 (Online); 0022-4456 (Print) |
| Appears in Collections: | JSIR Vol.74(11) [November 2015] |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| JSIR 74(11) 641-644.pdf | 168.88 kB | Adobe PDF | View/Open |
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